1. Field of the Invention
The present invention relates to a method and a device for reading out image data of a sub-range of an image, and to an image sensor including such a device. More precisely, the present invention relates to a method and a device for reading out image data of a sub-range of an image which is detected by an image sensor including a plurality of image sensor elements which can be read out by means of an activation signal sequentially appliable to the image sensor elements according to a predetermined clock signal.
2. Description of Prior Art
Modern industrial and consumer image capturing systems require evermore special image capturing algorithms and image processing algorithms designed for the respective application, wherein it is desirable in some cases to read out sub-ranges within an image with, compared to the usual image rate, multiple speed. Examples of application for this are:                inspection and arrangement systems which, after an initialization and aligning phase, must only read out sub-regions of the entire image and continue to process same,        monitoring tasks in automotive systems, such as, for example, motor vehicle indoor identification, anti-theft and road identification systems, and        high-speed, object tracking and target tracking systems.        
A conventional system allowing the readout of a sub-range of an image is illustrated referring to FIG. 7. This system includes an image sensor matrix 700 including a plurality of image sensor elements being arranged in rows and columns and defining image elements (pixel). The sensor arrangement shown in FIG. 7 includes a sensor matrix including I rows and J columns, wherein I, J≧1. Via corresponding addressing elements 702 and 704, for example by applying an activation signal sequentially applied to the individual image sensor signals for the columns and rows, respectively, according to a clock signal, the entire sensor content is shifted into the readout register 706 and from there to a memory 708. By means of a readout algorithm 710, the desired sub-image data is then read out of the entire image store in the memory 708 for a subsequent production of the sub-image.
In the fields of application mentioned above, there is a large need for reconfigurable image processing systems reducing the bandwidth of the image sensor output signal to the transmission bandwidth required. Since in image processing, especially in high-resolution image sensors, a huge mass of image data accumulates, the regional readout, i.e. the illustration of sub-areas of an image of interest, leads to significant increases in performance of the entire system, since the transmission bandwidth is reduced at an increasing information content, such as, for example, in high-speed post-tracking applications, or at a constant information content (such as, for example, in a multiple regional readout).
Existing image capturing systems, similar to that described referring to FIG. 7, for being in control of the requirements mentioned above, require the external image memory 708 and the intelligent readout algorithm 710 causing the memory content to be read out with the desired window mask. The disadvantage of this arrangement is that in this case the bandwidth cannot be reduced by means of the existing image sensors, since the entire image including the regions of a disappearing information content always has to be read out due to the predetermined sensor readout architecture.
In addition, additional latency times (waiting periods) rendering the entire system slow, are produced by latch-registering the image, which is one reason for the fact that high speed requirements cannot be met with this.
If possible at all, realizing one of the functionalities described above with a system as is described referring to FIG. 7 is only possible at considerable costs.
EP 0 809 395 A2 describes an x-y addressable pixel sensor in which it is possible to limit the image output to an array of the pixel sensor and, by the resulting reduction of image pixels to be output per image output, to increase the image rate of the pixel sensor. In a first embodiment, the pixel sensor, apart from the actual x-y addressable pixel array, includes two serial shift registers for indicating the row address or column address, respectively, and a row or column address control, respectively, for controlling the two serial shift registers. The address controls enable initializing the serial shaft registers by writing a digital one at any position within the shift registers. From this position on, the shift registers only shift the digital one to a position in which the defined window range to be read out ends. In a second embodiment, it is described that the pixel sensor, apart from the actual x-y addressable pixel array, includes the two serial shift registers and additionally a row or column enable switch, respectively. In contrast to the first embodiment, the serial shift registers pass all the rows or columns, respectively, of the pixel array. The two enable switches are, however, designed to load a predetermined sequence of digital ones to enable respective rows and columns corresponding to the image array to be output.
U.S. Pat. 5,641,126 describes a single chip pixel sensor having a pixel array controlled by electronics on the chip, a timing and controlling circuit controlling the row electronics and column electronics of the pixel array. The row and column electronics, respectively, include latch memories, counters and decoders. The timing and controlling circuit, via the latch memories, inputs an initializing value into the counters defining the starting position of an array to be read out. The counters then go through adjacent values one after the other departing from the initialization value. The values in the counters are the row and column addresses of the current pixel to be read out. By counting the increments and decrements of the counters and resetting the value in the counters via the ledge memories, an array to be read out can be read out similarly to as has been the case in the first embodiment of the document previously mentioned.
DE 3744128 A1 describes a method and a circuitry for a programmed driving of CCD and photodiodes matrix arrays to allow recording only sub-ranges of an image of interest. The circuitry includes a CPU and a memory, the CPU writing channel programs including a row of channel blocks into the memory. A DMA controller transfers the channel blocks from the memory into channel registers in which a camera control word and a number with which the camera control word is to be transferred repeatedly are stored. Upstream of the semiconductor array included in the circuitry, there is a suitable logic device to adapt the control signals to the respective timing requirements of the semiconductor array. Consequently, a complicated logic device is used in the circuitry to allow that a programmable readout of the semiconductor array can be performed.
U.S. Pat. No. 526,871 describes an image sensor with a pixel array comprising a device for directly addressing individual pixels and a device for selectively varying the number of pixels which can be read out at any read cycle. In this way, the image sensor allows adjusting several resolutions by summarizing pixels to super pixels and further allows sampling the image in any way, similarly to the performance of the human eye when sampling the visual field. In the image sensor, the readout of the pixels is performed directly.
EP 0527004 A1 describes an image recording device having an image sensor, such as, for example, a CCD or MOS type array, a vertical sampling circuit, a horizontal sampling circuit, an output unit and a driver circuit. The selection of a window to be read out along a row, in the image recording device, is obtained by the fact that the driver circuit, in the horizontal sampling circuit, produces start and end synchronization pulses indicating from where to where in a row the analog signal is to be sampled. For a selection of the rows of the output window, the content of which is to be output, the vertical sampling circuit is formed as shift register, which contains a bit sequence indicating which rows are released for outputting. The driver circuit can offset the shift register of the vertical sampling circuit in a suitable starting state, the release sequence releasing subsequent rows one after the other until the output window has been read out completely.